| 摘要 |
PURPOSE: To improve resistance to soft error in a semiconductor memory. CONSTITUTION: A memory cell 10 is the "so-called" CMOS cell. P-type wells W1P, W2P and W3P and N-type wells W4N and W5N are formed in the major surface 5S of a semiconductor substrate 5 and are arranged in the order W2P, W4N, W1P, W5N and W3P. Driver transistors 11DN and 12DN are formed, respectively, in the wells W2P and W3P, and load transistors 11LP and 12LP are formed, respectively, in the wells W4N and W5N. Two access transistors 11AN and 12AN are formed in a single well W1P. N¬+-type impurity regions FN30 and FN10 forming one memory node are divided into different wells and N¬+-type impurity regions FN31 and FN11, forming the other memory node, are also divided into different wells.
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