Synthesizer of super-high frequency (SHF) signals, comprises a sampled phase-locked loop (SPLL) with an interferometric circuit as a phase detector

摘要

The synthesizer device comprises a phase-locked loop (PLL) with an input (I) for a reference signal from a source (14), an output (2), a phase detector in the form of five-ports interferometric circuit (15), a three-branch circuit (16-26) for computing the phase difference on the basis of powers at output ports (5,6,7) of the interferometric circuit, a filter-corrector (27), a digital-analog converter (28), and a voltage-controlled oscillator (VCO) controlled by the filtered signal. If a digital processing circuit (13) is utilized for computing the phase difference, a digital filtration can be performed in the same circuit and also the computing of the frequency error of power values at the output ports (5,6,7) of the interferometric circuit (15) so to implement a frequency locked loop in order to avoid a false frequency lock. The circuit for computing the phase difference comprises in each branch a power detector (16,17,18), a sampler-holder (19,20,21), an analog-digital converter (22,23,24), and a digital circuit (26) common to all branches. The filter-corrector (27) is a digital filter. The digital processing circuit (13) is a microprocessor, a digital signal processor, a digital circuit with discrete logic, a digital circuit with integrated logic, or a digital circuit with reconfigurable logic. The interferometric circuit (15) comprises 2-4, in particular 3, output ports. The device (claimed) comprises a circuit for monitoring the frequency lock, and the filter-corrector is reconfigurable according to the output of the monitoring circuit.