| 摘要 |
An inductor equivalent circuit is disclosed. The circuit comprises a reference current source, a first current mirror, a second current mirror, two operational amplifiers OP1 and OP2, a capacitor, a first transistor, a second transistor, a mirror resistor set, and a bypass current source in parallel with the capacitor. An input signal is through OP1 and second transistor to control the reference current source. The first mirror current is then feed-back a signal to the first transistor through an OP2. The current signal makes the drain current of the first transistor lags the input voltage signal by 90° due to the capacitor coupled with the first mirror current source. The mirror resistor set can be resistors having one common terminal grounded, and other terminals each, respectively, coupled with the first and the second transistor and the capacitor, or can be composed of transistors and all of them with gate property biased so that the transistors in the mirror resistor set are operated in an ohmic region. The second mirror current provides an output current of the inductor equivalent circuit for next cascade stage. |
