| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a partial product generation circuit and a multiplier which can accelerate a calculation speed. <P>SOLUTION: A first encoding circuit E<SB>j1</SB>generates control codes A<SB>1</SB>and A<SB>2</SB>which determine a multiplying factor (1 or 2 time(s)) of the partial product to a multiplicand corresponding to a bit Y<SB>2j</SB>and a bit Y<SB>2j-1</SB>of a multiplier. The second encoding circuit E<SB>j2</SB>generates a control code /ZDT which determines whether the value of the partial product is set at '0' or not corresponding to the bit Y<SB>2j</SB>and a bit Y<SB>2j+1</SB>of the multiplier, and the second control code A<SB>2</SB>. The third encoding circuit E<SB>j3</SB>generates control codes Sgn and /Sgn which determine a code of the partial product corresponding to the bit Y<SB>2j+1</SB>of the multiplier, and a bit inversion signal AsX. The control code /ZDT which requires a long time to be generated is processed at a post-circuit of a bit circuit P<SB>ji</SB>, thereby accelerates the calculation speed. <P>COPYRIGHT: (C)2004,JPO |
