发明名称 |
SIMULATION DEVICE AND SIMULATION MODEL GENERATION PROGRAM |
摘要 |
PROBLEM TO BE SOLVED: To provide a simulation device capable of performing performance verification retaining a possible abstraction degree of cache analysis on a single verification platform without requiring an ISS (instruction set simulator). SOLUTION: A software-mounted function is generated as a software model 6 operated on a verification environmental platform (processor B), a hardware-mounted function is established as an RTL/RTC model 2 or an operation model higher in abstraction degree than it, and the performance verification is performed on the processor B. An interface model 7 for delivering input and output data between models is provided among the models. COPYRIGHT: (C)2004,JPO
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申请公布号 |
JP2004013227(A) |
申请公布日期 |
2004.01.15 |
申请号 |
JP20020162048 |
申请日期 |
2002.06.03 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
SHINOHARA KATSUYA;MIZUNO MASANOBU;MOTOHARA AKIRA |
分类号 |
G06F17/50;G06F9/455;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
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