| 摘要 |
A ROM embedded DRAM provides ROM cells that can be programmed to a single state. The ROM cells include capacitors having a storage node. The storage node is processed to have a substantially high substrate leakage. The ROM cells, therefore, are hard programmed to a logic zero state. Bias techniques can be used to read un-programmed ROM cells accurately. As described, sense amplifier circuitry can be offset in one embodiment to default to the un-programmed state. In another embodiment, bias circuitry is coupled to bit lines to favor the un-programmed state. A differential pre-charge operation can also be used in another embodiment. |
