| 摘要 |
A method (Fig. 1) of programming a multi-level memory chip in which the firs t, or lowest, voltage memory state (11) through the next-to-last voltage memory state (01) are programmed by a plurality of programming pulses (P; 40-47) increasing incrementally in voltage (30), alternated with a plurality of verify pulses (V; 50-57), and in which the last, or highest, voltage memory state (00) of the memory cell is programmed with a programming pulse (60) of the threshold voltage required for charging the memory cell to the highest voltage memory state. The programming method provides accuracy in programmin g the intermediate memory states (10, 01) of the cell, while providing speed i n programming the last memory state (00) of the cell to increase the overall speed of the program~ming the memory cell.
|
