发明名称 Boundary scan circuit
摘要 An electronic device includes a first circuit, a second circuit, and a boundary scan circuit. The boundary scan circuit includes a boundary scan register having a first cell connected to an input node of the first circuit, and a second cell connected between an output node of the first circuit and an input node of the second circuit. The second cell has a latch flip-flop. The boundary scan circuit also includes an interface that enables and disables the latching operation of the latch flip-flop according to an input instruction code. While the latching operation is disabled, the output from the latch flip-flop to the second circuit remains unchanged. In this state, the boundary scan circuit can be used to test the first circuit without unintended effects on the second circuit.
申请公布号 US2004010740(A1) 申请公布日期 2004.01.15
申请号 US20030405489 申请日期 2003.04.03
申请人 TANAKA HITOSHI 发明人 TANAKA HITOSHI
分类号 G01R31/28;G01R31/3185;(IPC1-7):G01R31/28 主分类号 G01R31/28
代理机构 代理人
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