发明名称 |
Output circuit, input circuit, electronic circuit, multiplexer, demultiplexer, wired-or circuit, wired-and circuit, pulse-processing circuit, multiphase-clock processing circuit, and clock-multiplier circuit |
摘要 |
A circuit is provided to make the propagation delay time of each signal path substantially the same without using a low resistance process even when wiring lengths are different. In the circuit, output nodes a to d are individually disposed at the output side of transmission gates TG2, TG4, TG6, and TG8, these output nodes a to d are connected so as to have an equal wiring length, inverters IV11 and IV12 are disposed at the output nodes a and d, and a common node e is disposed at a position where the wiring length from each of the inverters IV11 and IV12 becomes identical.
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申请公布号 |
US2004008073(A1) |
申请公布日期 |
2004.01.15 |
申请号 |
US20030359021 |
申请日期 |
2003.02.05 |
申请人 |
KOZAKI MINORU |
发明人 |
KOZAKI MINORU |
分类号 |
H01L21/82;H03K5/00;H03K5/14;H03K5/15;H03K5/1534;H03K17/00;H03K19/0175;H03K19/0948;H03K19/20;(IPC1-7):G06G7/16 |
主分类号 |
H01L21/82 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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