| 摘要 |
PURPOSE: A method for forming a high voltage transistor is provided to decrease junction depth while reducing channel width. CONSTITUTION: After forming an isolation layer(43) at the inner portion of a semiconductor substrate(41) having a high voltage well(42), a buffer oxide layer and an ion implantation mask are sequentially formed at the upper portion of the resultant structure. After carrying out an ion implantation at the resultant structure, a drift region(47) is formed at an active region of the semiconductor substrate by carrying out an annealing process at the resultant structure. After depositing a nitride layer at the upper portion of the resultant structure, a channel region of the semiconductor substrate is exposed by selectively patterning the resultant structure. Then, a trench is formed by etching the exposed channel region. A gate electrode(45) is formed at the trench. Then, a gate spacer(46) and a source/drain region(48) are sequentially formed at the predetermined portions of the resultant structure.
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