| 摘要 |
A clock synchronization device includes: a coarse delay line arranged to sequentially delay an external clock signal and output one or more pairs of first multi-phase clock signals and one or more pairs of second multi-phase clock signals; a clock interface arranged to select a pair of clock signals having opposite phases from among the one or more pairs of first multi-phase clock signals and the one or more pairs of second multi-phase clock signals and further arranged to synthesize the phase of a pair of the selected clock signals; and a fine delay line arranged to finely delay the pair the selected clock signals from the clock interface and output an internal clock signal synchronized with the external clock signal.
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