发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURING METHOD
摘要 PURPOSE: To reduce the threshold voltage of a planar capacitor at the same time by controlling the thresholds of respective MOS transistors without increasing the number of processes in a semiconductor integrated circuitdevice having the planar capacitor and using a plurality of power source voltages. CONSTITUTION: The semiconductor integrated circuit device comprises a p-channel memory transistor and the capacitor formed on an first n-type element region, an n-channel low voltage MOS transistor formed on a second p-typeelement region, and an n-channel high voltage MOS transistor formed on a third p-type element region. Channel doping is performed with a high concentration profile by a p-type impurity element on the channel region of a second MOS transistor, and at the same time, the p-type impurity element is substantially introduced with the same profile on the first element region.
申请公布号 KR20040004058(A) 申请公布日期 2004.01.13
申请号 KR20030040148 申请日期 2003.06.20
申请人 FUJITSU LIMITED 发明人 ANEZAKI TORU
分类号 H01L27/04;H01L21/822;H01L21/8234;H01L21/8242;H01L27/06;H01L27/10;H01L27/105;H01L27/108;(IPC1-7):H01L27/10 主分类号 H01L27/04
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