| 摘要 |
Abstract of Disclosure A cache control device comprises a command control section 43 for receiving a cache deterioration report and generating a cache flush mode initiation signal which performs degeneration of the cache 44, a software interrupt section 52 for interrupting the supply of commands from software in response to the cache flush mode initiation signal, a command generating section 53a for generating fetch requests in which cache data flushing occurs to the cache in response to the cache flush mode initiation signal, an address generating section 54 for generating addresses for flushing the cache data in response to the cache flush mode initiation signal, and a request counter 58 for specifying ways at which flushing of the cache will be performed, whereby degeneration is possible where different CPUs are mounted in the system, or where a CMP micro architecture is employed, without the necessity of changing the system hardware or OS, or making additions to the computer architecture.
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