| 摘要 |
An integrated MOS power transistors, in particular a lateral PMOS power transistor and a lateral n-DMOS power transistor, in which the bulk node is disposed in a manner spatially isolated from the source electrode zone. The particular integration structure of the MOS power transistor avoids a parasitic drain-bulk diode, a parasitic body diode and a substrate diode and thereby achieves an area-saving protection against over-currents in the event of reverse voltage polarity between drain and source.
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