| 摘要 |
The invention relates to a semiconductor circuit configuration and to an associated fabrication method, in which a semiconductor substrate has a plurality of word lines and a plurality of bit lines for the row by row and column by column driving of a matrix of switching elements. In this case, a plurality of electrically conductive connection strips for connecting source and drain regions in the active region to the respective bit lines are formed between the word lines such that they directly make contact with the source and drain regions at the surface of the semiconductor substrate in the active region. In this way, a particularly compact cell area is obtained in conjunction with very simple lithographic conditions.
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