发明名称 |
LAYOUT METHOD OF SEMICONDUCTOR DEVICE |
摘要 |
PROBLEM TO BE SOLVED: To easily and quickly develop and evaluate a semiconductor device by improving the work efficiency in layout and shortening the layout time. SOLUTION: Before a layout of a semiconductor device, maximum values of wiring resistance and wiring capacity of wiring are computed by simulation. The semiconductor device layout is then designed so that the wiring resistance and capacity do not exceed the computed values. COPYRIGHT: (C)2004,JPO
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申请公布号 |
JP2004005193(A) |
申请公布日期 |
2004.01.08 |
申请号 |
JP20020159782 |
申请日期 |
2002.05.31 |
申请人 |
TOSHIBA CORP;TOSHIBA MICROELECTRONICS CORP |
发明人 |
HARA MASAYUKI |
分类号 |
G06F17/50;H01L21/82;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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