发明名称 |
EMBEDDED VERTICAL DRAM CELLS AND DUAL WORKFUNCTION LOGIC GATES |
摘要 |
A process for producing very high-density embedded DRAM/very high-performance logic structures comprising fabricating vertical MOSFET DRAM cells with salicided source/drain and gate conductor dual workfunction MOSFETs in the supports, comprising: Forming a french capacitor in a silicon substrate having a gate oxide layer, a polysilicon layer, and a top dialectric nitride layer deposited thereon; Applying a patterned mask over the array and support areas and forming recesses in the nitride layer, the polysilicon layer, and shallow trench isolation region; Forming a silicide and oxide cap in the recesses in the nitride layer, the polysilicon layer, and shallow trench isolation region; Applying a block mask to protect the supports while stripping the nitride layer from the array and etching the exposed polysilicon layer to the top of the gate oxide layer; Striping the nitride layer from the support region and depositing a polysilicon layer over the array and support areas; Applying a mask to pattern and form a bitline diffusion stud landing pad in the array and gate conductors for the support transistors; Saliciding the tops of the landing pad and the gate conductors; Applying an interlevel oxide layer and then opening vias in the interlevel oxide layer for establishing conductive wiring channels. |
申请公布号 |
WO0245130(A3) |
申请公布日期 |
2004.01.08 |
申请号 |
WO2001US44625 |
申请日期 |
2001.11.28 |
申请人 |
INFINEON TECHNOLOGIES NORTH AMERICA CORP.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
GRUENING, ULRIKE;DIVAKARUNI, RAMACHANDRA;MANDELMAN, JACK;RUPP, THOMAS |
分类号 |
H01L27/10;H01L21/8242 |
主分类号 |
H01L27/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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