发明名称 |
Scaled mosfet device and its fabricating method |
摘要 |
A scaled MOSFET device of the present invention comprises a shallow-trench-isolation structure being formed on a semiconductor substrate; a conductive-gate structure having a pair of second conductive sidewall spacers formed over each inner sidewall of a gate region and on a first conductive layer and first raised field-oxide layers for forming an implant region in a central portion of a channel and a planarized third conductive layer for forming a salicide-gate structure or a polycide-gate structure; a buffer-dielectric layer being formed over each sidewall of the conductive-gate structure for forming lightly-doped source/drain diffusion regions; a first sidewall dielectric spacer being formed over each sidewall of the buffer-dielectric layers for forming heavily-doped source/drain diffusion regions; and a second sidewall dielectric spacer being formed over each sidewall of the first sidewall dielectric spacers for forming a self-aligned silicidation contact over each of the heavily-doped source/drain diffusion regions.
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申请公布号 |
US2004004259(A1) |
申请公布日期 |
2004.01.08 |
申请号 |
US20020188051 |
申请日期 |
2002.07.03 |
申请人 |
INTELLIGENT SOURCES DEV CORP |
发明人 |
WU CHING-YUAN |
分类号 |
H01L21/28;H01L21/336;(IPC1-7):H01L29/76 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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