| 摘要 |
A spare column on which spare memory cells are arranged is provided in a memory cell array. In the memory cell array, address assignment can be altered so that sub-word lines selected collectively according to the same row address is divided into the right and left halves. The alteration in assignment can be realized by disconnecting a fuse element incorporated in a SD generating circuit. Even in a case where a plurality of defective memory cells are concentrated on the same memory cell row, the number of defective memory cells in a select unit corresponding to row address can be altered by alteration in address assignment so as to be reduced as a result of distribution; thereby enabling increase in number of chips that can be saved with spare memory cells. Accordingly, improvement on saving rate for defective chips can be realized without increasing the number of spare memory cells.
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