发明名称 SYSTEM AND METHOD FOR AVOIDING STALL OF AN H-ARQ REORDERING BUFFER IN A RECEIVER
摘要 A system and method for avoiding stall of an H-ARQ reordering buffer in a receiver is disclosed. The present invention reduces the latency of the H-ARG reordering buffers within a receiver and uses a Last-In-First-Out (LIFO) policy for loading the transmitting H-ARQ processors. The LIFO loading policy increases the probability that the UE will be able to determine at an earlier time whether the missed TSN is due to delay in retransmission of due the release of a transmission by the Node B by reading the new H-ARQ processor identifier (ID).
申请公布号 WO2004004188(A2) 申请公布日期 2004.01.08
申请号 WO2003US20037 申请日期 2003.06.25
申请人 INTERDIGITAL TECHNOLOGY CORPORATION 发明人 CHAO, YI-JU
分类号 H04L1/18;H04L12/56 主分类号 H04L1/18
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