| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a NAND cell type EEPROM having a cell array for achieving high-speed random reading and a sense-amplifying circuit, without increasing a chip area. <P>SOLUTION: The NAND cell type EEPROM has a memory cell array where a memory cell unit is arranged in a matrix, where the memory cell unit comprises a first selection MOS transistor STD for allowing a NAND cell where a plurality of nonvolatile memory cell arrays are connected in series to make conductive a bit line; and a second selection MOS transistor STS for allowing the NAND cell to make conductive a source line. In the NAND cell type EEPROM, a first memory cell unit, where the threshold of STD is larger than that of STS and a second memory cell, where the threshold of STD is smaller than that of STS share a gate electrode in each STD and each STS, to compose a subarray. <P>COPYRIGHT: (C)2004,JPO</p> |
