发明名称 Methods and structure for hiding DRAM bank precharge and activate latency by issuing apriori bank state transition information
摘要 In a system having multiple master devices coupled to a shared resource, methods and structure for generating apriori information by an arbiter of the shared resource to enable the shared resource to better utilize the bandwidth of the shared resource. A first preferred embodiment of the invention provides an arbiter coupling a shared memory controller to a plurality of master devices generating memory requests for the memory controller. The arbiter preferably detects memory requests from another master device to detect when a next request is directed to a different bank of memory. Apriori information indicative of such a change in banks is sent to the memory controller in advance of the memory request that will require the change of banks. This apriori information enables the memory controller to control the sequence of commands applied to the memory subsystem to optimize utilization of the memory subsystem and hence improve system performance.
申请公布号 US2004006665(A1) 申请公布日期 2004.01.08
申请号 US20020188881 申请日期 2002.07.02
申请人 MOSS ROBERT W. 发明人 MOSS ROBERT W.
分类号 G06F13/16;(IPC1-7):G06F12/00 主分类号 G06F13/16
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