| 摘要 |
PURPOSE: A method for manufacturing a DRAM memory cell is provided to be capable of reducing the area of DRAM cells of planar structure by using simple layout. CONSTITUTION: A dual gate oxide layer is formed on a silicon substrate(100) having an isolation layer(102). A capacitor electrode(108) is formed on the resultant structure. After forming a spacer(110) at both sidewalls of the capacitor electrode, a source/drain region(112) is formed in the substrate. After forming a silicide layer(114) on the capacitor electrode, an interlayer dielectric(116) is formed on the resultant structure. A bit line contact hole is formed by selectively etching the interlayer dielectric. A metal plug(118) is then formed by filling metal into the bit line contact hole.
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