| 摘要 |
PURPOSE: A semiconductor test circuit is provided to increase test efficiency by reducing function test time and the number of pins used in the test in a DRAM test circuit. CONSTITUTION: A control part(20) operates by receiving /RAS(Row Address Strobe) and /CAS(Column Address Signal) and an address control signal. A DRAM cell(21) comprises a plurality of memory cells which are selected selectively by receiving a control signal of the control part. An output buffer(22) reads data of a selected cell of the DRAM cell part. A latch(23) stores a specific number of data. The first logic circuit part(24) compares the value read in the DRAM cell part with the value stored in the latch part by comparing the value read from the DRAM cell part with the data stored in the latch part. And the second logic circuit part(25) compares the value read from the DRAM cell part with the data stored in the latch part by receiving an output of the first logic circuit part as an input and then outputs it to one external pin.
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