发明名称 |
PROCESSOR ARCHITECTURE |
摘要 |
A processor architecture includes a plurality of processing elements and a bus structure. Each element has at least one input port and at least one output port, each port having at least a data bus and a valid data signal line. The bus structure contains a plurality of switches arranged to connect an output port of any first processing element to the input port of any second processing element for a time interval. Each processing element sets a value on the valid data signal line of its output port to a first logic state when the associated data bus contains a transfer value and to a second logic state when it does not contain a transfer value. Each processing element enters a waiting state for a predetermined time interval when the value on the valid data signal line of the associated input port is in the second logic state. |
申请公布号 |
EP1377911(A2) |
申请公布日期 |
2004.01.07 |
申请号 |
EP20010976500 |
申请日期 |
2001.10.19 |
申请人 |
PICOCHIP DESIGNS LIMITED |
发明人 |
CLAYDON, ANTHONY, PETER, JOHN |
分类号 |
G06F7/00;G06F1/32;G06F9/38;G06F13/36;G06F15/80;(IPC1-7):G06F15/78 |
主分类号 |
G06F7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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