| 摘要 |
PURPOSE: A method for fabricating a semiconductor device is provided to prevent ions from penetrating a gate oxide layer through an oxide layer spacer in a subsequent process by forming a spacer structure of the first nitride layer, an oxide layer and the second nitride layer on the sidewall of a gate electrode and by forming the third nitride layer as a barrier layer after a chemical mechanical polishing(CMP) process is performed to isolate the landing plug in a cell part. CONSTITUTION: A gate electrode having a hard mask layer(39) in its upper portion is formed by interposing a gate oxide layer(33) on a semiconductor substrate(31) where the cell part and a peripheral part are defined. A spacer wherein the first nitride layer, the oxide layer and the second nitride layer are sequentially stacked is formed on the sidewall of the hard mask layer and the gate electrode. An interlayer dielectric(47) is formed and planarized on the resultant structure. The interlayer dielectric is etched to form a contact hole for the landing plug by a photolithography process using a make for a landing plug contact in the cell part. A conductive layer is formed and etched back. The conductive layer and the interlayer dielectric are etched to form the mutually isolated landing plugs in the cell part by a CMP process using the hard mask layer as an etch end point wherein the spacer is exposed. The third nitride layer is formed on the interlayer dielectric including the exposed spacer.
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