| 摘要 |
PURPOSE: A method for fabricating a bitline of a semiconductor device is provided to reduce bitline parasitic capacitance and prevent the refresh of a chip from being decreased by forming an air layer in a space between bitline such that the air layer has a dielectric constant smaller than that of a SiO2-based interlayer dielectric. CONSTITUTION: The first interlayer dielectric(33) having a plurality of the first contact holes for the bitline(35) is formed on a substrate. A plurality of mutually isolated bitlines are formed on the first interlayer dielectric, burying the first contact holes, respectively. The first insulation layer having poor step coverage is formed on the resultant structure wherein the first insulation layer is deposited in the upper portion of the space more than in the lower portion of the space to generate a void between the bitlines. The second interlayer dielectric(43) as a planarization layer is formed on the first insulation layer wherein the second interlayer dielectric is formed on the void like a cover. The second interlayer dielectric, the first insulation layer and the first interlayer dielectric are etched to form a storage node contact hole by a photolithography process using a storage node contact mask. The second insulation layer spacer is formed on the inner wall of the storage node contact hole.
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