METHOD FOR FABRICATING GATE IN DUAL GATE LOGIC DEVICE

摘要

PURPOSE: A method for fabricating a gate in dual gate logic device is provided to prevent damage to a gate oxide layer and an active region by thickening a portion of the gate oxide layer having a high etching rate. CONSTITUTION: A gate region of the first conductivity type and a gate region of the second conductivity type are defined in a substrate. A gate oxide layer(10) and a polysilicon layer(20) are stacked on the substrate. An additional blocking layer is formed on the polysilicon layer. An additional mask is formed on the additional blocking layer. The additional blocking layer is patterned to expose the gate region of the second conductivity type by using the additional mask. The additional mask is eliminated. A compensational silicon layer(50) is formed on the polysilicon layer in the exposed gate region of the second conductivity type having an etch rate faster than that of the gate region of the first conductivity type. The remaining blocking layer is eliminated. A patterning process is additionally performed to form a gate of the first conductivity type and a gate of the second conductivity type wherein the gates have the same height.