| 摘要 |
PURPOSE: A semiconductor integrated circuit comprising a scan flip flop is provided, which has a test device to detect an error of embedded glue logics and has low power consumption. CONSTITUTION: The semiconductor integrated circuit(100) comprises a macro circuit block(108), and the first glue logics(104,105,112,113) providing signals to be inputted to the above macro circuit block. The first scan flip flops correspond to the first glue logics respectively, and have a data input port receiving a data signal being output from the corresponding first glue logic and a clock input port receiving the second clock signal. And a clock gating circuit provides the second clock signal to the first scan flip flops in response to a scan mode signal.
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