| 摘要 |
PURPOSE: A method for forming a single damascene pattern of a semiconductor device is provided to reduce an etching process for low dielectric insulating material by carrying out a photolithography process for a damascene structure using predetermined resist containing silicon. CONSTITUTION: After sequentially forming a resist pattern and an SiOx layer at the upper portion of a semiconductor substrate(100), a copper layer is formed on the entire surface of the resultant structure. A copper line(130a) is formed by carrying out a CMP(Chemical Mechanical Polishing) process at the copper layer until the resist pattern is exposed. After removing the resist pattern, a low dielectric insulating layer is formed at the upper portion of the resultant structure. Then, an interlayer dielectric(140a) is formed by carrying out the CMP process at the low dielectric insulating layer.
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