| 摘要 |
PURPOSE: A method for manufacturing a semiconductor device is provided to reduce the resistance of a gate electrode by increasing the surface area of a silicide layer. CONSTITUTION: A plurality of gate electrodes(25) are formed at the upper portion of a silicon substrate(5). The first oxide layer(30) and a nitride layer(40) are sequentially formed at the upper portion of the resultant structure. After forming the second oxide layer at the resultant structure, the second oxide layer is etched until the nitride layer is exposed. Then, the nitride layer located at the upper portion of the gate electrode, is etched. An NMOS(N channel Metal Oxide Semiconductor) transistor is formed by implanting P ions into an NMOS region. After forming an N+ and P+ region at the resultant structure, a silicide layer(60) is formed at the upper portion of each gate electrode for completely enclosing the upper portion of the gate electrode.
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