| 摘要 |
PURPOSE: A method for forming a flash memory cell is provided to increase coupling ratio of a floating gate by enhancing the surface area of the floating gate. CONSTITUTION: A tunnel oxide layer(11), the first floating gate(12) and a self-aligned isolation layer(13) are sequentially formed on a silicon substrate(10). The second floating gate(14) is formed on the resultant structure. The second floating gate(14) is selectively etched to isolate the isolation layer using a photoresist pattern. By isotropic etching of the exposed isolation layer(13), the lower portion of the second floating gate is exposed. By removing the photoresist pattern, a floating gate is then formed.
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