发明名称 |
Majority vote circuit for test mode clock multiplication |
摘要 |
A circuit configured to generate an output clock signal generally having (i) a first frequency when in a first mode and (ii) a second frequency when in a second mode, in response to a plurality of signals. At least one of the plurality of signals may comprise an identical signal path while in the first mode and the second mode.
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申请公布号 |
US6675312(B1) |
申请公布日期 |
2004.01.06 |
申请号 |
US20000609192 |
申请日期 |
2000.06.30 |
申请人 |
CYPRESS SEMICONDUCTOR CORP. |
发明人 |
BAKER WILLIAM G. |
分类号 |
G06F1/08;(IPC1-7):G06F1/08 |
主分类号 |
G06F1/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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