发明名称 Exception handling for SIMD floating point-instructions using a floating point status register to report exceptions
摘要 A method, apparatus, and computer program product for handling IEEE 754 standard exceptions for Single Instruction Multiple Data (SIMD) instructions. Each SIMD sub-operation's corresponding IEEE 754 exception flag is bit-wise "ORed" with an accrued exception field if a trap enable mask field is configured to mask the exception, with the "ORed" result written back in the accrued exception field. If the trap enable mask field is configured to enable the exception, the accrued exception field and a current exception field are cleared, and an unfinished floating-point exception flag is set in a floating-point trap type field. The actual sub-operation(s) causing the exception is determined through software.
申请公布号 US6675292(B2) 申请公布日期 2004.01.06
申请号 US19990374052 申请日期 1999.08.13
申请人 SUN MICROSYSTEMS, INC. 发明人 PRABHU J. ARJUN;PRIEST DOUGLAS M.
分类号 G06F9/38;(IPC1-7):G06F15/00 主分类号 G06F9/38
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