发明名称 Process for forming damascene-type isolation structure for integrated circuit
摘要 Isolation of a heterojunction bipolar transistor device in an integrated circuit is accomplished by forming the device within a trench in dielectric material overlying single crystal silicon. Precise control over the thickness of the initially-formed dielectric material ultimately determines the depth of the trench and hence the degree of isolation provided by the surrounding dielectric material. The shape and facility of etching of the trench may be determined through the use of etch-stop layers and unmasked photoresist regions of differing widths. Once the trench in the dielectric material is formed, the trench is filled with selectively and/or nonselectively grown epitaxial silicon. The process avoids complex and defect-prone deep trench masking, deep trench silicon etching, deep trench liner formation, and dielectric reflow steps associated with conventional processes.
申请公布号 US6674144(B1) 申请公布日期 2004.01.06
申请号 US20020269125 申请日期 2002.10.11
申请人 NATIONAL SEMICONDUCTOR CORPORATION 发明人 ESSAIAN STEPAN
分类号 H01L21/331;H01L21/762;(IPC1-7):H01L27/095;H01L29/00;H01L27/082 主分类号 H01L21/331
代理机构 代理人
主权项
地址