| 摘要 |
The voltage output terminals of a semiconductor integrated circuit are connected to the first ends of resistors while the second ends of the resistors are connected to a common signal line. Taking advantage that the potential of the signal line presents the mean voltage value of the voltages output from all the voltage output terminals, the deviation of the potential at each voltage output terminal from the mean value and the difference of this mean value from the ideal value are determined, whereby the suitability of the output voltage from each of the output terminals is examined.
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