发明名称 |
Block redundancy implementation in hierarchical RAMs |
摘要 |
<p>The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines (3202) or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder (3200A-3200D) adapted to be shifted out of use; and at least one redundant predecoder (3200E) adapted to be shifted in to use.</p> |
申请公布号 |
EP1376610(A2) |
申请公布日期 |
2004.01.02 |
申请号 |
EP20030014062 |
申请日期 |
2003.06.23 |
申请人 |
BROADCOM CORPORATION |
发明人 |
TERZIOGLU, ESIN;WINOGRAD, GIL I.;AFGHAHI, MORTEZA CYRUS |
分类号 |
G06F13/40;G11C7/06;G11C7/18;G11C11/419;G11C29/00;(IPC1-7):G11C29/00;G11C11/417 |
主分类号 |
G06F13/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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