发明名称 Systems and methods for time-budgeting a complex hierarchical integrated circuit
摘要 Systems and methods for time-budgeting an integrated circuit design are provided. A representative system includes an information acquisition device, a computer, and a memory element associated with the computer, the memory element configured to store the information and associate a timing point that accounts for signal delays between the border of a functional block and the various circuits within the block. A representative method includes the following steps: acquiring circuit information that describes the conductors that traverse a border of the functional block, inserting a timing point in the information, determining a delay time in response to the timing point, and deriving a constraint in response to the delay time.
申请公布号 US2004003360(A1) 申请公布日期 2004.01.01
申请号 US20020180632 申请日期 2002.06.26
申请人 BATCHELOR DENNIS B.;MIELKE DAVID JAMES 发明人 BATCHELOR DENNIS B.;MIELKE DAVID JAMES
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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