| 摘要 |
Disclosed here is a data processor provided with an addressing mode for calculating each effective address from the displacement (reference address) included in the subject instruction and the information retained in an index register allocated to a general-purpose register so as to minimize an increase of the logical/physical scale. The value in the index register is increased so as to be shifted according to the memory access size, for example, by one when the memory access size is byte and by two when the memory access size is word. Because both extension and shifting are included in the effective address calculation, the number of instructions, as well as the number of execution states are reduced. And, because the array size is smaller than the address space size, the upper part of each general-purpose register is used as a data register, thereby the data amount to be written in each general-purpose register is increased and the number of times for reading/writing from/in the subject memory is reduced. Consequently, the number of instructions is further reduced, thereby the program capacity is reduced.
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