发明名称 Decoding circuit for wafer burn-in test
摘要 A decoding circuit for a wafer burn-in test internally generates a strobe signal during the wafer burn-in test by using external input address signals, thereby decreasing the number of input pads required to receive external input strobe address signals. A plurality of pulse generating units respectively delay and logically combine a plurality of external input address signals to generate pulses. Thereafter, an internal strobe signal is generated by respectively delaying and logically operating the pulses from the pulse generating units.
申请公布号 US2004000932(A1) 申请公布日期 2004.01.01
申请号 US20020331287 申请日期 2002.12.30
申请人 JANG JI EUN 发明人 JANG JI EUN
分类号 G11C8/10;G11C29/00;G11C29/20;(IPC1-7):H03K19/173 主分类号 G11C8/10
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