发明名称 |
Debug interface for an event timer apparatus |
摘要 |
An on-chip event timer apparatus including a hardware timer and a debug interface. The hardware timer includes at least an up-counter for counting clocks of a clock signal, a match register for storing a programmable count value, and a comparator for monitoring whether the up-counter's count value matches the count value of the match register. The debug interface includes enable control unit for enabling the up-counter's operation based on a pre-defined relationship between a state of an enabled signal supplied to said up-counter and an internal state of the hardware timer. Additionally, the debug interface may comprise a clock divider connected to the enable control unit to reduce the clock's frequency in accordance with a pre-programmed divider value. Based on the received clock with the reduced clock frequency, the enable control unit adapts the up-counter's processing speed to the reduced clock frequency.
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申请公布号 |
US2004003027(A1) |
申请公布日期 |
2004.01.01 |
申请号 |
US20030361089 |
申请日期 |
2003.02.07 |
申请人 |
ROLLIG RENE;MEYER JENS;BARTH FRANK;KREBS ALEXANDER |
发明人 |
ROLLIG RENE;MEYER JENS;BARTH FRANK;KREBS ALEXANDER |
分类号 |
G06F1/14;G06F11/36;(IPC1-7):G04F1/00 |
主分类号 |
G06F1/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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