| 摘要 |
A clock divider of a DLL circuit for generating an internal clock signal synchronized to an external clock signal is disclosed which includes a first clock divider for generating a first clock signal dividing a clock signal having the same period with the external clock signal, a second clock divider for generating a second clock signal and a third clock signal by dividing the first clock signal, a selection signal generator for generating a selection signal in response to a plurality control signals and a clock signal selector for selectively outputting the second clock signal or third clock signal in response to the selection signal.
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