发明名称 Instruction fetch control apparatus
摘要 When an instruction stored in a specific instruction buffer is the same as another instruction stored in another instruction buffer and logically subsequent to the instruction in the specific instruction buffer, a connection is made from the instruction buffer storing a logically and immediately preceding instruction, not the instruction in the other instruction buffer, to the specific instruction buffer without the instruction in the other instruction buffer, and a loop is generated by instruction buffers, thereby performing a short loop in an instruction buffer system capable of arbitrarily connecting a plurality of instruction buffers.
申请公布号 US2004003202(A1) 申请公布日期 2004.01.01
申请号 US20030347193 申请日期 2003.01.21
申请人 FUJITSU LIMITED 发明人 UKAI MASAKI
分类号 G06F9/38;(IPC1-7):G06F9/30 主分类号 G06F9/38
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