| 摘要 |
PURPOSE: A method for fabricating complementary metal oxide semiconductor(CMOS) transistor is provided to maximize a current flow by arbitrarily controlling the junction depth of a source/drain. CONSTITUTION: N-type impurities are selectively injected into a PMOS transistor formation portion of a p-type semiconductor substrate(10) to form an N-well(11). After a silicon oxide layer(12) is deposited on the semiconductor substrate, the silicon oxide layer in a channel formation region is patterned. A single crystal silicon layer(13) is grown on the channel formation region by an epitaxial growth process. The first polysilicon layer(14) that is not doped is grown on the silicon oxide layer. A thick field oxide layer(15) is formed on an interface between the silicon substrate and the N-well. A gate oxide layer(16) and the second polysilicon layer(17) are formed on the resultant structure having the field oxide layer and are patterned to form a gate. A low density impurity ion implantation process is performed. After a spacer(18) is formed on the side surface of the gate, a high density impurity ion implantation process is performed. An interlayer dielectric(19) is deposited on the resultant structure. After an etch process is performed until the silicon oxide layer is sufficiently exposed to form a contact hole, a metal barrier layer(20) is deposited. Tungsten is deposited on the metal barrier layer and is etched back to form a tungsten plug(21). After all of the tungsten on the interlayer dielectric is eliminated by an etch-back process, a metal interconnection(22) is formed.
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