| 摘要 |
A logic circuit comprising an input (11) for one or several input operands (A, B), an output (15) for a result (C) and an inverted result (C), a first circuit branch (19), comprising a first logic arrangement (20), which is coupled to the input (11) and the output (15), in order to calculate the result (C), in addition to a second circuit branch (21), comprising a second logic arrangement (22), which is coupled to the input (11) and output (15) in order to calculate the inverted result (C). The first logic arrangement (20) and the second logic arrangement (21) have different run times in order to calculate the result (C) or inverted result (C). The invention also relates to a time delay circuit or compensation circuit (24) provided in the first and/or second circuit branch (19,21) in order to reduce the difference in run times or power consumption of the first and second circuit branches (19,21), thereby obtaining a higher degree of security against hardware attacks. |
