| 摘要 |
A PLL circuit according avoids any large change in a frequency in a VCO (5) even if an input horizontal synchronization signal suddenly changes or a level of the frequency decreases to a predetermined value or less, or disappears. The PLL circuit comprises a switch (3) to be provided on an output side of a phase comparator (2) to control an output voltage of the VCO by connecting to an AFC filter (4) and supplying a phase difference current according to a phase difference, during the time the horizontal synchronization signal is supplied. The comparator (2) compares a phase of an Hin signal through a delay circuit (1) with a phase of a return (RET) signal through a dividing circuit (6) and a delay circuit (7) from the VCO. With this structure, the comparator does not supply any phase difference current and does not make the VCO change at the time when the Hin signal is disappeared. The comparator controls the VCO by means of supplying the phase difference current to have a time length according to a pulse width of the Hin signal or less for a higher frequency of the Hin signal and according to a delay time length given by the delay circuit (1) for a lower frequency of the Hin signal.
|
