发明名称 M & A FOR DYNAMICALLY DETERMINING AND MANAGING CONNECTION TOPOLOGY OF AN HIERARCHICAL SERIAL BUS ASSEMBLY
摘要 Circuitry and complementary logic are provided to a bus controller (14), a number of 1:n bus signal distributor (18), and a number of bus interfaces (22) of a hierarchical serial bus assembly for the bus controller to dynamically detect and manage the interconnection topology of the serial bus elements. The serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logi c support a hierarchical view of the serial bus elements (16), logically dividing the hierarchy into multiple tiers. This logical view of t he serial bus elements is used by the bus controller to detect the presence of interconnected serial bus elements and the functions of the bus agents, i.e. the system unit and the interconnected peripheral, as well as assignment of addresses to the serial bus elements and the functions, at power on, reset, and during operation when serial bus elements are hot attached to or detached from the serial bus assembly.</SDOA B>
申请公布号 CA2202517(C) 申请公布日期 2003.12.30
申请号 CA19952202517 申请日期 1995.10.31
申请人 INTEL CORPORATION 发明人 KNOLL, SHAUN;CADAMBI, SUDARSHAN BALA;MORRISS, JEFF CHARLES;BHATT, AJAY V.;CALLAHAN, SHELAGH
分类号 G06F12/06;G06F13/38;H04L12/64;(IPC1-7):G06F13/20 主分类号 G06F12/06
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