发明名称 |
Efficient arrangement of interconnection resources on programmable logic devices |
摘要 |
Interconnection block arrangements for selectively interconnecting logic on a programmable logic device is provided. Programmable logic connectors within the interconnection blocks may be programmed to route signals between the various conductors on the device and to route signals from various logic regions on the device to the various conductors. The interconnection blocks are arranged to optimize the use of metallization resources and to increase interconnectivity and logic density.
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申请公布号 |
US6670825(B1) |
申请公布日期 |
2003.12.30 |
申请号 |
US20020319320 |
申请日期 |
2002.12.13 |
申请人 |
ALTERA CORPORATION |
发明人 |
LANE CHRISTOPHER F.;POWELL GILES V.;YEUNG WAYNE;SUNG CHIAKANG;PEDERSEN BRUCE B. |
分类号 |
H03K19/177;(IPC1-7):H03K19/177 |
主分类号 |
H03K19/177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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