发明名称 Manufacturing process evaluation method for semiconductor device and pattern shape evaluation apparatus using the evaluation method
摘要 First wiring pattern data corresponding to a shape of a wiring pattern on a layer in a semiconductor device is acquired on the basis of a first image obtained by imaging a sample which permits imaging of the wiring pattern. Evaluation CAD data which synthesizes CAD data of a plurality of layers, which includes wiring CAD data of the layer with the wiring pattern is generated. Position coordinates of the first wiring pattern data are made to coincide with position coordinates of a wiring pattern contained in the wiring CAD data, and synthesis data is produced by synthesizing the first wiring pattern data and the evaluation CAD data. Based on the synthesis data, a degree of overlapping between the first wiring pattern data and a pattern in the CAD data of a layer other than the layer with the wiring pattern is quantized.
申请公布号 US6671861(B2) 申请公布日期 2003.12.30
申请号 US20020107426 申请日期 2002.03.28
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 NODA TOMONOBU
分类号 G01B21/00;G06F17/50;G06T1/00;G06T7/00;H01L21/66;(IPC1-7):G06F17/50 主分类号 G01B21/00
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