| 摘要 |
Embodiments of the invention provide a direct landing technology for improved wafer testing of semiconductor dies that is scalable to next generation packaging. In particular, the package drawing or custom drawing of a semiconductor die under test is infused on the printed circuit board of the sort interface unit. After decoupling capacitors are mounted and a semiconductor die footprint fabricated on printed circuit board sort interface unit, probe head may be directly sandwiched between semiconductor die under test and printed circuit board sort interface unit. Since the package information is infused on the printed circuit board sort interface unit, the need for a multi layer ceramic space transformer, sockets and so forth are eliminated and high speed testing facilitated. The manufacturing process becomes extremely simplified, low cost, and more reliable due to significantly reduced variable dependencies.
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